`timescale 1ns/1ns

module calculation(
           input clk,
           input rst_n,
           input [3: 0] a,
           input [3: 0] b,
           output [8: 0] c
       );
reg [8: 0] b_1;
reg [8: 0] a_8;
reg [8: 0] a_4;
reg [8: 0] b_4;
reg [3: 0] a_r, b_r;
always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				a_r <= 4'd0;
				b_r <= 4'd0;
			end
		else
			begin
				a_r <= a;
				b_r <= b;
			end
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				a_8 <= 9'd0;
				a_4 <= 9'd0;
				b_1 <= 9'd0;
				b_4 <= 9'd0;
			end
		else
			begin
				a_8 <= {2'd0, a_r, 3'd0};
				a_4 <= {3'd0, a_r, 2'd0};
				b_1 <= {5'd0, b_r};
				b_4 <= {3'd0, b_r, 2'd0};
			end
	end

assign c = a_4 + a_8 + b_1 + b_4;
endmodule
